Phase-shift keying electronic circuit with distributed structure

ABSTRACT

The invention concerns a modulating electronic circuit with m phase status m≧2 comprising a distribution line (6) with n similar dephasing cells (Ci) n≧2, each comprising a transistor supplying on a derivative output (ODi) an out-of-phase signal (SDi); a secondary switching/modulating stage (4) controlled on the basis of a control signal; means for summing in phase the signals derived the switching/modulating stage (4).

The invention concerns a phase-shift keying modulator circuit (so-calledPSK "phase Shift keying" or MDP "modulation de phase").

Such circuits are used in particular for the transmission of digitalsignals. For example, the transmission of digital signals between asatellite and earth can be effected by phase modulation of a microwavecarrier signal by a digital signal.

Binary phase-shift keying (BPSK/or MDP2) or quadrature phase-shiftkeying (QPSK/or MDP4) modulator circuits are already known ("HIGH BITRATE FOUR PHASE MMIC REMODULATION DEMODULATOR AND MODULATOR", A.Primerose et al., Proceedings of GAAS '92, Estec, Nordwich, TheNetherlands). A BPSK circuit can thus be formed by a low-pass filter anda high-pass filter mounted in parallel and whose outputs are switched toa common output by an array of two shunted MESFET transistors whosegates receive complementary, two-state signals. This circuit has theadvantage of supplying a phase shift between the signals, which ofcourse by design tends towards the theoretical value of 180°, despiteinevitable manufacturing imperfections. Furthermore, the MESFETtransistors used for switching are not biased and the circuit introducesonly small losses (of the order of 3 dB). It can be realised in MMICtechnology and requires little space (typically 2 mm×1 mm for 8 GHz).Nevertheless, such a BPSK circuit has the drawback of a large spectralbandwidth for a given bit timing. Moreover, it does not include anyelectrical control means and does not allow phase shifts with valuesother than 180°, so that it cannot be used in certain applications whena residual carrier with non-zero amplitude is required(to synchronize areceiver for example).

A QPSK circuit formed from two BPSK circuits allows a smaller spectralbandwidth for the same bit timing, but still has the disadvantages ofabsence of adjustment means based on an electrical control and onlyallows phase shifts of a fixed value. Furthermore, these circuitsgenerate larger losses (of the order of 8 dB) and have overalldimensions of the order of 2.5 mm×3.5 mm at 8 GHz.

πn/4-QPSK circuits are also known ("π/4-QPSK MODEMS FOR SATELLITESOUND/DATA BROADCAST SYSTEMS", Chiu-Liang Liu, Kassilo Feher, IEEETransactions on broadcasting, vol. 37, No. 1, March 1991, pp 1-8) whichare circuits with eight phase states obtained by additional π/4 phaseshifts at each phase change. These circuits have the same disadvantagesas the above-mentioned traditional QPSK circuits. It should also benoted that of the eight possible phase states, only certain phasetransitions are allowed, so that the π/4-QPSK circuits are onlycompatible with an appropriate coding system, and in particular cannotbe used with certain types of digital signal coding to be transmitted.

The document "A VERSATILE VECTOR MODULATOR DESIGN FOR MMIC", L. M.Devlin, B. J. Minnis, 1990 IEEE MTT-S Digest L-7 pp 519-522, describes a2×four phase state modulator circuit, that is to say producing twovectorial signal structures with different amplitudes. This circuit hasoverall dimensions of 4 mm×3 mm at 8 GHz, and has four variableresistances whose adjustment is complex. Moreover, it is functionallyequivalent to a QPSK circuit, since the eight phase states, not havingthe same amplitude, are not useable for basic phase modulation (withoutamplitude modulation) with eight phase states.

With the aim of reducing the power during the transmission, an attemptis made to use high-performance digital signal coding such as TCM(trellis-coded modulation). To do this, it is essential to havemodulation circuits having a number of phase states greater than four(in particular 8, 16 . . . ).

Now it is not conceivable to combine the architecture of the known BPSKor QPSK arrangements in the same circuit with the aim of improving bitrate performance since the imperfections of each component affect theothers and accumulate at the output. Moreover, a crippling loss of powerresults, particularly for systems on board aircraft and spacecraft.Furthermore, the very costly manufacturing refinements would bemultiplied.

The invention therefore aims to overcome these drawbacks by proposing aPSK modulator circuit whose structure enables phase states of any valueto be obtained, with a zero or low power loss and with a low energyconsumption, so that this circuit can be adapted and used with numeroustypes of coding and phase modulation and in numerous applications.

The invention furthermore aims to propose a modulator circuit whosenumber of phase states can be greater than four (with the same amplitudeand the same frequency), in particular equal to eight, sixteen . . . .

The invention furthermore aims to propose such a PSK modulator circuitwhich is advantageously suited to construction using microwavemonolithic technology (MMIC)--particularly on gallium arsenide(GaAs)--with excellent precision.

More specifically, the invention aims to propose a PSK modulator circuithaving simple means for setting the phase states, in particular inaccordance with the frequency of the input signal, so as to permit itscharacteristics to be adjusted in relation to the system in which it isincorporated, and this at the same time as its incorporation in thesystem (and not at the time of its design or of the manufacture of thePSK integrated circuit itself).

The invention furthermore aims more specifically to propose such a PSKmodulator circuit that is compatible with the constraints of on-boardspace systems (compact dimensions, excellent reliability, lowconsumption . . . ).

The invention also aims more specifically to propose such a PSKmodulator circuit that is compatible with high bit rate modulationcoding systems such as TCM.

The invention also aims more specifically to propose such a PSKmodulator circuit that is able to be adapted to any carrier signalfrequency, in particular in the microwave region.

The invention also aims more specifically to propose such a PSKmodulator circuit that, once produced, can accept incoming carriersignals whose frequency is fixed, but can also be selected within a wideband (for example in the X band or the Ka band for earth observationtelmetering, in the K band of multimedia telecommunication satellites .. . ).

The invention furthermore aims to propose such a PSK modulator circuitthat does not produce any appreciable interference to the line or theinput signal.

To achieve this, the invention concerns an electronic phase-shift keyingmodulator circuit comprising an input intended to receive a sinusoidalinput signal Se of angular frequency we and an output delivering asinusoidal output signal Ss phase shifted with respect to the inputsignal by a value φj which can vary among m values, φ1, . . . , φj, . .. , φm, m being an integer greater than or equal to 2, in accordancewith a control signal SCj, the output signal Ss having an angularfrequency ωs that is independent of the control signal Scj, wherein saidcircuit comprises:

a distribution line extending from the input and including n cells Co, .. . , Ci, . . . , Cn-1, of similar phase shift, n being a whole numbergreater than or equal to 2, the n phase-shift cells being mounted alongthe distribution line with each phase-shift cell Ci of rank i along thedistribution line comprising:

an input, referred to as the series input ISi, receiving the signalcoming from the input of the circuit, either directly where i=0, or via(i-1) preceding phase-shift cells of rank less than i, interposedbetween the input of the circuit and this phase-shift cell Ci,

a first output, referred to as the series output OSi, delivering thesignal on the distribution line to a subsequent phase-shift cell Ci+1 ofhigher rank i+1, or, where i=n-1, to a terminating device of thedistribution line,

a tapping point Ni of the distribution line,

a second output, referred to as the branched output ODi, connected tothe tapping point Ni via a transistor Ti whose first terminal isconnected to the tapping point Ni, whose second terminal is connected toground, and whose third terminal supplies said branched output ODi ofthe phase-shift cell Ci, each phase-shift cell Ci being designed todeliver at its branched output ODi a signal SDi that is phase shiftedwith respect to the input signal Se, by the sum φ(Ci) of the phaseshifts successively applied to the input signal Se, from the input ofthe circuit by the phase-shift cells interposed between the input of thecircuit and said branched output ODi,

connected to said branched output ODi of each phase-shift cell Ci, aswitching/modulating circuit controlled by the control signal SCj, thisswitching/modulating circuit being:

when n=m, a switching circuit delivering either a zero signal, or thesignal SDi received from the cell Ci, in accordance with the controlsignal SCj,

when n≠m, a modulating circuit with p phase states, p being a wholenumber less than m chosen so that m≦p^(n), designed to phase-shift thesignal SDi received from the phase-shift cell Ci by a value φk, k beinga whole number varying between 1 and p, in accordance with the controlsignal SCj,

means for summing in phase the signals Ssi coming from nswitching/modulating circuits and to deliver at said output of thecircuit the result of this sum which forms the output signal Ss.

A circuit according to the invention thus has a distributed type ofstructure. This structure provides a great number of adaptation options.In particular, the number n of phase-shift cells can be optimized inrelation to the number m of desired phase states. The phase shiftapplied to the signal by each phase-shift cell and, if need be, by eachmodulator circuit with p phase states, can also be optimized.

Throughout this patent application, the expression "similar phase-shiftcells" signifies that the cells are composed of electronic componentshaving the same electronic functions, even if the structure and thevalues of these components differ from cell to cell. Moreover, theexpression "functionally identical phase-shift cells" denotesphase-shift cells which are similar and which are designed to normallyinduce exactly the same phase shift in the signal between their inputand their outputs.

It should be noted that the modulator circuits with p phase states usedat the output of the phase-shift cells can themselves have a distributedstructure according to the invention. In that way the invention enablesthe production of "multi-stage" modulator circuits comprising severalcascaded PSK phase-shift stages.

In practice, it can be seen that this distributed structure effectivelyallows adequate precision to be obtained for each phase state in orderto realise a circuit--in particular by the use of MMIC technology--witheight phase states, or indeed even more.

Advantageously and according to the invention, the circuit comprisesmeans for biasing the transistors of the phase-shift cells. Each PSKphase-shift stage is therefore amplified by these transistors, whichprovide gain to the signal.

Furthermore, advantageously and according to the invention, each of saidtransistors is a field-effect transistor--in particular MESFET (onGaAs)--whose:

first terminal is the gate,

second terminal is the source,

third terminal is the drain.

The field-effect transistors have an input conductance whose real partis very low, which puts little load on the distribution line, and thusallows a virtually identical level to be obtained at each of the tappingpoints and at each branched output. All the downstreamswitching/modulating circuits are therefore supplied with the samesignal level.

Moreover, the switching/modulating circuits of each branch are isolatedfrom each other by the field-effect transistors and do not mutuallyinterfere (for example, if each switching/modulator circuit is a BPSKtype, the SWRs (standing wave ratios) of the BPSK circuits at thechange-of-state rate run no risk of degrading the accuracy of thestates.

Equally, the field-effect transistors isolate the line and the inputsignal, which is not disturbed by the switching operations induced bythe circuit.

Furthermore, a circuit according to the invention comprises means forapplying a DC voltage whose value is adjustable at the tapping point Ni,so as to form an adjustable capacitance between the tapping point Ni andground. In fact, the field-effect transistors have a non-linear inputcapacitance that can be adjusted by the gate bias voltage. This variablecapacitance, in parallel with the distribution line, enables thephase-shift generated by each cell to be adjusted. That allows theaccuracy of the phase states to be improved and the risks of pooroperation associated with the circuit production process to beminimized.

Advantageously, a circuit according to the invention has the featurewherein each phase-shift cell Ci is of a series inductance and parallelcapacitance type, wherein said transistor of each phase-shift cell Ci isa biased field-effect transistor whose gate is connected to the tappingpoint Ni on the distribution line in parallel with the inductance, whosesource is connected to ground, and whose drain supplies the branchedsignal SDi to said branched output , and wherein said parallelcapacitance is at least partially made up of the capacitance formedbetween the gate and the source of said biased field-effect transistor.

Furthermore, advantageously and according to the invention, all thephase-shift cells are functionally identical and generate the same phaseshift Δφ along the distribution line, the cell Ci delivering at itsbranched output a branched signal SDi that is phase-shifted with respectto the input signal Se by φ(Ci)=i×Δφ+ψ, where ψ is a constant. Thisphase-shift Δφ, identical for all the cells, can be equal to 2π/m, ordifferent from 2π/m (if an output signal with a mean value other thanzero is required).

Furthermore, advantageously and according to the invention, the meansfor applying and adjusting a DC voltage whose value is adjustable ateach tapping point Ni include a terminal of the distribution lineintended to receive a DC voltage so that the phase shifts of the signalat each tapping point Ni of the phase-shift cells Ci can be adjustedsimultaneously, in particular in accordance with the angular frequencyωe , by setting this one variable DC voltage. It should be noted thatMMIC technology is particularly well adapted to this simultaneousadjustment of all the LC phase-shift cells, since the transistors of thesame chip have very little leakage, so that the input capacitances ofthe transistors are equal and vary in the same way with the bias.

Advantageously and according to the invention, said means for summing inphase comprise, particularly when n=m, star-connection lines from theoutputs of n switching/modulating circuits to a common output point andall these branching lines have the same length, so as to present aconstant output impedance, generally 50 Ohms.

Furthermore, advantageously and according to the invention, andparticularly when n≠m, said means for summing in phase include a phasecombiner circuit formed by a Wilkinson coupler tree, the final apex ofwhich forms said output of the circuit. The advantage of Wilkinsoncouplers is to isolate said p state phase modulator circuits from eachother at the output end. These circuits are thus isolated from the inputend by the transistors of the phase-shift cells and at the output end bythe Wilkinson couplers.

Advantageously and according to the invention, when m is a multiple of apower of 2, n is made equal to a power of 2. In this way, the Wilkinsoncoupler tree has an axial symmetry with respect to the output of thecircuit (since each Wilkinson coupler has two inputs and one output).

Advantageously, a circuit according to the invention has the featurewherein

m is greater than or equal to 4,

p is equal to 1, 2 or 4.

Advantageously, a circuit according to the invention has the featurewherein

m is greater than or equal to 8,

n is greater than or equal to 4.

More generally, n is advantageously greater than or equal to m/2. Thenumber of phase states of the modulator circuits at the output of thephase-shift cells can thus be minimized (in particular equal to 2).

Moreover, advantageously and according to the invention, theswitching/modulating circuits are similar and consist exclusively ofpassive components. Throughout this patent application "passivecomponents" are all components mounted so as not to require anyadditional electrical power supply for their operation (resistors,inductors, capacitors, non-biased transistors . . . ).

Advantageously, and particularly when m is a multiple of 2, a circuitaccording to the invention has the feature wherein p=2 and wherein theswitching/modulating circuits are binary phase-shift keying BPSKcircuits with passive components, each formed by a high-pass filter anda low-pass filter mounted in parallel and whose outputs are switched bya non-biased field-effect transistor array with their gate receiving acontrol signal having two complementary states. The p phase state phasemodulator circuits are thus traditional BPSK circuits (p=2).

Moreover, advantageously, a circuit according to the invention comprisesmeans forming a variable impedance at one end terminal of thedistribution line opposite to the input of the circuit, to allow itsimpedance matching.

Advantageously and according to the invention, the variable impedancecomprises a field-effect transistor configured as a variable resistance,and whose gate receives a DC control voltage.

Advantageously and according to the invention, a circuit according tothe invention has a feature wherein the frequency of the input signal isgreater than 1 Gigahertz and said circuit is formed from a monolithicintegrated circuit.

The invention also extends to a circuit wherein it includes incombination all or some of the characteristics mentioned above or below.

Other aims, features and advantages of the invention will be revealed inthe following description of non-restricting exemplary embodiments ofthe invention, and which refers to the accompanying figures, in which:

FIG. 1 is a schematic view of the entire circuit according to theinvention,

FIG. 2 is a schematic view of an embodiment of a circuit according tothe invention, where m=8, n=4, p=2,

FIG. 3 is a schematic view of an embodiment of the binary phase-shiftkeying BPSK modulator circuit of FIG. 2,

FIGS. 4 and 5 are Fresnel diagrams showing two examples of the vectorialconstruction in the complex plane of the output signal of the circuit ofFIG. 2,

FIG. 6 is a Fresnel diagram showing in the complex plane an 8 phasestate configuration of the output signal that can be obtained with thecircuit of FIG. 2,

FIG. 7 is a schematic view of an embodiment of a circuit according tothe invention, where m=n=2 and p=1.

A circuit according to the invention shown in a general way in FIG. 1comprises an input 1 intended to receive, in the form of an electriccurrent, an input signal Se=Asin(ωet+φe) and an output 2 intended todeliver, in the form of an electric current, an output signalSs=A'Sin(ωst+φs) phase modulated according to a control signal SCj thatis generally a digital signal or represents a digital signal.

The circuit according to the invention is a phase-shift keying (PSK/ orMDP) modulator circuit with m phase states, that is to say the outputsignal Ss is phase-shifted with respect to the input signal by a valueφj=φs-φe, which may vary among m values φ1, φ2, . . . , φj, . . . , φm,m being a whole number greater than or equal to 2.

By contrast, the bit timing ωs of the output signal is independent ofthe control signal SCj, and is generally identical to ωe. The circuitaccording to the invention is particularly suited to the processing ofsignals in the microwave range (conventionally from 1 GHz to 300 GHz)where propagation phenomena are significant. Nevertheless, the inventionis also applicable to the production of phase modulator circuits in allfrequency ranges.

In the embodiments shown, by preference and according to the invention,the amplitude A' of the output signal can vary in relation to thecontrol signal SCj, but it is not generally used as a modulationparameter. Nevertheless, the circuit according to the invention is alsocompatible with amplitude modulation combined with phase modulation,either with the aid of a modulation coding system which uses thedifferent amplitude states that can be obtained with the circuitaccording to the invention in certain configurations, or by use ofsupplementary means for amplitude modulation arranged upstream and/ordownstream of the circuit according to the invention.

From the upstream end to the downstream end (that is to say from theinput 1 up to the output 2) the circuit according to the inventionbasically comprises three successive stages, i.e.: a primarydistribution/modulation stage 3 comprising a distribution line 6, atleast one secondary switching/modulating stage 4, and a multiplexingstage 5 at the output 2.

The distribution line 6 enables the signal to be distributed to a numberof n branches B0, B2, . . . , Bi, . . . , Bn-1, by applying a primaryphase shift φ(Ci) depending on the rank i of the branch Bi. Thedistribution line 6 thus comprises n cells C0, C1, . . . , Ci, . . . ,Cn-1 of similar phase shift, mounted end to end in a ladderconfiguration to define the n branches. The number n is a whole numbergreater than or equal to 2 (the distribution line 6 contains at leasttwo phase-shift cells in order to distribute the signal to at least twobranches) and is preferably less than or equal to m.

Each phase-shift cell Ci of rank i of the distribution line 6 comprises:

an input, referred to as the series input ISi, receiving the signalcoming from the input 1 of the circuit, either directly where i=0, orwhere i≠0 via (i-1) preceding phase-shift cells of lesser rank,interposed between the input 1 of the circuit and this phase-shift cellCi,

a first output, referred to as the series output OSi, connected, wherei≠n-1, to the series input ISi+1 of a subsequent phase-shift cell Ci+1of higher rank i+1 or, where i=n-1, to a terminating device 7 of thedistribution line 6, said series output OSi delivering a signal,referred to as the series signal SSi,

a second output, referred to as the branched output ODi, connected toone of the branches Bi corresponding to said phase-shift cell Ci, saidbranched output ODi delivering a signal referred to as the branchedsignal SDi.

Each phase-shift cell Ci is designed to apply a phase shift, referred toas the series phase shift φSi between the signal that it receives at itsseries input ISi (which is the series signal SSi-1 delivered by the cellCi-1 immediately upstream on the line) and the signal SSi which itdelivers to its series output OSi, and to apply a phase shift, referredto as the branched phase shift φDi, between the signal that it receivesat its series input ISi and the signal SDi which it delivers to itsbranched output ODi.

The phase shift of the series signal SSi with respect to the inputsignal Se is equal to ##EQU1##

The phase shift φ(Ci) presented by the branched signal SDi applied tothe branch Bi by the cell Ci with respect to the input signal Se iswritten: ##EQU2##

Each phase-shift cell Ci is advantageously formed by a low-pass LCfilter with series inductance and parallel capacitance, and includes atapping point Ni at which the signal, with respect to the series inputsignal ISi, presents a phase shift that depends on the value of theseries inductance interposed between the series input ISi and thetapping point Ni and on the total parallel capacitance formed betweenthe tapping point Ni and ground.

The phase-shift cells Ci form, between the input 1 and the terminatingdevice 7, a distribution line configuration 6, which can be consideredas an L or T or π configuration, according to the branches (with orwithout series inductance) of the first tapping point No with respect tothe input 1 and of the last tapping point Nn-1 with respect to theterminating device 7 of the distribution line 6.

FIG. 2 represents a configuration that can be considered as a Tconfiguration. The tapping point Ni is connected to the branched outputODi of the cell Ci via a field-effect transistor To, . . . , Ti, . . . ,Tn-1, whose gate is directly connected to the tapping point Ni, whosesource is directly connected to ground and whose drain is connected tothe branched output ODi. Each transistor Ti is biased so that saidparallel capacitance of the phase-shift cell Ci is at least partiallymade up of the capacitance formed between the gate and the source of thetransistor Ti. In the embodiment of FIG. 2, the parallel capacitance ofeach phase-shift cell Ci is formed exclusively by the transistor Ti. Inthe embodiment of FIG. 5 an additional capacitor 8, 9 is interposedbetween each tapping point and ground.

Each phase-shift cell Ci contains means 10, 11 for biasing itstransistor Ti, for example in the form of a surge inductance 10 one ofwhose terminals is connected to the drain of the transistor Ti and whoseother terminal receives a fixed DC bias voltage VP, and a blockingcapacitor 11 connected in series between the drain and the branchedoutput ODi.

With such an arrangement, the value of the capacitance formed betweenthe gate and the source is non-linear and depends on the DC gate biasvoltage. The circuit according to the invention therefore includes means12 for applying a DC voltage of adjustable value, after production ofthe circuit, to each tapping point Ni. These means 12 can simply consistof a terminal 12 of the distribution line 6 designed to be able toreceive an adjustable DC voltage VA formed by voltage generation meansexternal to the circuit. An isolating capacitor 16 is provided upstreamof the input 1 to isolate the source generating the input signal(generally an oscillator) from the DC voltage VA.

It should be noted that, as a variant or in combination, bias voltagesVP can be used to adjust the value of the phase shifts created by thephase-shift cells Ci.

In the embodiment of FIG. 2, advantageously and according to theinvention, the distribution line 6 contains a number of inductancesarranged in series from the input 1 of the circuit to the terminatingdevice 7, separated from each other by the tapping points No, . . . ,Ni, . . . , Nn-1, to which the gates of the transistors Ti areconnected. The inductance L between two tapping points is shown splitinto two parts L/2 to show that each part of this inductance forms arespective functional part of each corresponding phase-shift cell (shownby the broken lines) and the T configuration thus obtained.

Advantageously and according to the invention, all the phase-shift cellsCo to Cn-1 are functionally identical and generate the same seriesphase-shift φSi and the same phase-shift φDi from their series input ISialong the distribution line 6.

Thus, for all the ranks i between 1 and n-1, the phase differenceφ(Ci)-φ(Ci-1)=Δφ between the branched signals SDi and SDi-1 delivered bythe cells Ci and Ci-1 which adjoin each other along the distributionline, is the same along the distribution line 6.

Advantageously and according to the invention, Δφ=2π/m. In other words,φ(Ci)=ixΔφ+ψ=2πi/m+ψ, where ψ is a constant. In that way, the signal Ssat the output of the circuit will have a mean amplitude (with respect totime) of zero (the circuit supplying modulation without a residualcarrier).

When the circuit is being designed, with an appropriate choice of thevalue of L and of the transistors, it is easy to obtain suitable valuesfor the primary phase-shifts applied to the input signal by thephase-shift cells Ci. Furthermore, these phase-shifts can be adjustedsimultaneously after production of the circuit by applying a suitablevoltage VA which enables the gate-source capacitance of the transistorsto be varied.

It should be noted that this structure is particularly suited toproduction using monolithic technology--especially MMIC--all thetransistors being identical, having low leakage and equal capacitancesvarying in the same way with VA.

The terminating device 7 contains an isolating capacitor 28, two seriesresistors 13, 14 and a field-effect transistor 15 configured as avariable resistance, whose drain is star-connected between the twoseries resistors 13, 14, whose source is grounded and whose gatereceives a DC control voltage VR. A variable resistance is thus formedthat is able to be adjusted by the electrical parameter VR, which easilyallows the impedance of the distribution line 6 to be matched, inparticular to take account of variations in the voltage VA and in theparallel capacitances formed by the transistors Ti of the phase-shiftcells Ci, and technological variations in the resistors 13, 14 duringproduction.

It should be noted that the distribution line 6, and particularly thephase-shift cells Ci, can be realised differently from a ladderconfiguration of LC circuits (for example delay lines, bridged Tarrangements . . . ), since each phase-shift cell Ci delivers a branchedsignal SDi phase-shifted by a value φ(Ci) which is appropriate to itwith respect to the input signal Se.

In accordance with the control signal SCj, the secondaryswitching/modulating stage 4 enables branched output signals Ssi to beformed from n branched signals SDi delivered by the phase-shift cells Ciat their branched output ODi.

This secondary switching/modulation stage 4 thus comprises aswitching/modulating circuit Mi connected to the branched output ODi ofeach phase-shift cell Ci at each branch Bi, that is to say a total of nswitching/modulating circuits M0, . . . , Mi, . . . , Mn-1.

The stage 4 can be composed, particularly if n=m, of simple in-phaseswitching circuits delivering at the output a signal SSi that is eithereach branched signal SDi or a zero signal, depending on the state or thevalue of the control signal SCj.

In particular if n≠m, the stage 4 consists of phase modulator circuitsMi with p phase states, p being a whole number chosen so that m≦pn andp<m. Therefore these circuits are themselves of the PSK type, but havinga much smaller number of phase states p than the circuit according tothe invention. Each phase modulator circuit Mi is designed tophase-shift the branched signal SDi which it receives a value φk, kbeing a whole number varying between 1 and p in accordance with thecontrol signal SCj.

In practice and in general, it is desirable to minimize p to simplifythe construction and obtain reliable circuits and low consumption andlosses. Advantageously, (preferably if m is a multiple of 2, which isthe most common case) p=2 and the modulator circuits Mi are BPSK types.

Such is the case with the embodiment of FIG. 2, where n=4 and p=2, themodulator circuits M0, M1, M2, M3 being BPSK types produced in theconventional manner in accordance with the diagram shown in FIG. 3. Eachcircuit M0 to M3 is formed by a T type low-pass LC filter 17 and a Ttype high-pass LC filter 18 connected in parallel downstream of an inputterminal 19, and whose outputs are switched and combined in phase at acommon output terminal 20 by a parallel configuration of two unbiasedswitching field-effect transistors 21, 22, having one terminal connectedto the output of the corresponding filter 17, 18, one terminal connectedto ground, and receiving via their gate a control signal with twocomplementary states so that only one of the two transistors 21, 22 isconducting at the time and the transistor 21, 22 conducting for thefirst state of the control signal is turned off for the second state.The signals emerging from the filters and switched in this way arecombined in phase by the combiner 23, with star-connected inductancesand matching parallel capacitance, at the output terminal 20. A seriesmatching inductance 24 is provided between the input terminal 19 and thefilters 17, 18. Such a BPSK circuit is itself known and has theparticular advantage of a phase shift which tends naturally to 180°, andof being able to be constructed on an integrated circuit of the MMICtype.

As a variant, a BPSK circuit which itself conforms to this invention(for example according to a diagram similar to that shown in FIG. 5) cancertainly be employed in the circuit of FIG. 2.

The control signal SCj contains n components of p states and thereforerepresents a digital signal able to assume p^(n) values. Nevertheless,the signals Ssi coming from n switching/modulating circuits Mi arecombined in phase at the output 2 with the aid of the multiplexing stage5. Consequently, the output signal Ss sometimes only represents a numberm<p^(n) phase states (for certain values of n, of p and of φ(Ci) thesignals may cancel each other and/or the phase states may be repeated).

A control signal SCji is applied to each switching/modulating circuitMi, and this signal SCji is one of the components SCji of the controlsignal SCj.

Each of the modulator circuits Mi delivers a branched output signal Ssi,the phase of which is therefore φi=φ(Ci)+φk.

φk varies with the control signal SCj, and more specifically with thecomponent SCji of the control signal, which is applied to the modulatorcircuit Mi. Preferably, all the modulator circuits Mi are identical anddesigned so that φk=2πk/p.

In the embodiment of FIG. 2, the control signal SCji is made up of fourcomponents SCj0, SCj1, SCj2, SCj3, which are the voltages representinglogic levels, each being able to assume two complementary values U0, U0;U1, U1, U2, U2; U3, U3.

The branched output signals Ss0, Ss1, Ss2, Ss3 can be represented in thecomplex plane by vectors I, U, Q, V, and each can assume twophase-shifted values of 180°, corresponding to the vectors I, -I; U, -U;Q, -Q; V, -V, respectively.

The multiplexing stage 5 is composed of means for summing in phase(vectorial sum) the signals SSi and for delivering at the output 2 ofthe circuit the result of this vectorial sum, which forms the outputsignal Ss. These means comprise an in-phase combiner circuit formed by aWilkinson coupler tree (in-phase power couplers), the final apex ofwhich forms said output 2 of the circuit.

In the case of FIG. 2 where n=4, the multiplexing stage 5 includes threeWilkinson couplers 25, 26, 27, that is to say two couplers 25, 26 of afirst series coupling the signals SSi in pairs and a second seriescoupler 27 receiving the signals emerging from the first series couplers25, 26 and delivering the output signal Ss at the output 2.

If the inductances L and the field-effect transistors T0, T1, T2, T3 andVA are chosen so that Δφ=π/4, the output signal Ss is represented in thecomplex plane by a vector Ss which describes a double signal structureof 8 phase states. The first signal structure corresponds to signals Sswith amplitudes greater than those of the second signal structure. FIG.4 shows an example of the construction of an output signal Sscorresponding to the first signal structure, obtained when all thebranched output signals Ssi are phase-shifted in pairs by π/4, that isto say when the control signal SCj assumes the following values:

    ______________________________________                                                SCj0 SCj1         SCj2   SCj3                                         ______________________________________                                        SC1        I      U            Q   -V                                         SC2        I      U            Q    V                                         SC3       -I      U            Q    V                                         SC4       -I     -U            Q    V                                         SC5       -I     -U           -Q    V                                         SC6       -I     -U           -Q   -V                                         SC7        I     -U           -Q   -V                                         SC8        I      U           -Q   -V                                         ______________________________________                                    

In theory, with this first structure, A'/A 32 2.613.

The second signal structure, of which an example of the construction ofthe signal Ss is represented in FIG. 5, corresponds to the case where atleast one pair of branched output signals which adjoin each other in thecomplex plane, are phase-shifted by π/2. It corresponds to the othereight possible values of the 16 values (2⁴ =p^(n)) of the control signalSCj.

In theory, with this second signal structure, A'/A=1.082.

Consequently, although the circuit in fact delivers sixteen outputsignal states, these sixteen states correspond to only eight phasestates (and two amplitude states in a ratio of 7.66 dB).

The circuit of FIG. 2 can be used for the transmission of digitalsignals by a microwave carrier signal (input signal Se) (a frequencybetween 1 GHz and 300 GHz) phase modulated according to TCM coding. Inthis case, preferably only the first signal structure is used at maximumamplitude, so as to minimize the modulator losses. In this respect itshould be noted that the transistors T0, T1, T2, T3 of the phase-shiftcells C0, C1, C2, C3 of the branches B0, B1, B2, B3 are biased andreduce the losses, indeed even provide a gain between the input 1 andthe output 2.

In order to select the first signal structure it is sufficient toprovide a transcoder circuit between the 3-bit coded digital signal (8states) and the 4-bit coded signal SCj, of which only 8 combinations areapplied to the modulators Mi.

The circuit of FIG. 2 can be realised using MMIC technology and, for afrequency of 8 GHz, has dimensions of the order of 4.3 mm×4.1 mm,supplying eight true phase states, indeed even sixteen phase states ifΔφ≠π/4 is chosen (for example where Δφ=π/8).

FIG. 6 represents an example of a signal structure that can be obtainedwith the circuit of FIG. 2, where ωe/2π=8 GHz. In this diagram eachpoint represents the end of the vector representing the output signalSs, its amplitude (in dB) and its phase (in degrees) being indicated.

FIG. 7 illustrates a second embodiment where the circuit according tothe invention is a BPSK type with two phase states containing twophase-shift cells C0, C1 defining two branches B0, B1, so that m=n=2.

This embodiment provides additional capacitors 8, 9 connected betweentapping point N0, N1 and ground. The distribution line 6 comprisesseries inductances L/2, an input capacitor 16, a terminating capacitor28, resistors 13, 14 and the transistor 15 configured as a variableresistance to form the terminating device 7, two field-effecttransistors T0, T1 with their bias inductance 10 and bias capacitor 11.

In this embodiment, the switching/modulating stage 4 contains twoswitching circuits CO0 and CO1 each comprised of two unbiasedfield-effect transistors 29, 30, 31, 32, of which the first 29, 31 isconnected in parallel with its source connected to ground via a seriesresistor and its drain connected to the branch B0, B1, and the second30, 32 connected in series with the source connected to the drain of thefirst transistor 29, 31, and whose drain supplies the branched outputsignal Ss0, Ss1. The gates of the transistors 29, 30, 31, 32 receive thetwo-state voltages U, U formed from the control signal SCj, which canitself assume two complementary states U, U, so that when SCj=SC1=U, thesignal Ss0 on the first branch is not zero and is equal to the signalcoming from the phase-shift cell C0, while the signal Ss1 on the secondbranch is zero (the transistors 30 and 31 being conducting while thetransistors 29 and 32 are turned off). And vice versa, when SCj=SC2=U,the transistors 30, 31 are turned off while the transistors 29, 32 areconducting, so that the signal Ss0 is zero and the signal Ss1 is thesignal emerging from the phase-shift cell C1.

Said means 5 for summing in phase the branched output signals Ss0, Sslare simply formed from two lines 33, 34 of the same length and arestar-connected downstream of the two outputs of the switching circuitsCO0 and CO1 formed by the transistors 29, 30, 31, 32. The two lines 33,34 are joined together at an output point forming the output 2 of thecircuit, which therefore receives alternatively either the signal Ss0 orthe signal Ss1, depending on the state of the control signal SCj.

The inductances L, the capacitance of the capacitors 8, 9, thetransistors T0, T1 of the phase-shift cells C0, C1 and the adjustingvoltage VA can be chosen so that Ss1 is phase-shifted by any value, evendifferent from 180°, with respect to Ss0. A BPSK circuit with any valueof phase shift is therefore obtained.

For example, the phase shift can be made a value other than 180° toobtain a bi-phase modulator with residual carrier for long-distancelinks having very low bit rates for planetary probes.

The invention is particularly advantageous for the production ofmicrowave circuits (MMIC). It is, nevertheless, also applicable forphase shift modulation in other frequency ranges.

Furthermore, the invention is also applicable for the production ofm-PSK circuits with distributed structure, which differ from thoserepresented and described above, in particular with other values of m, nand p.

Moreover, it should be noted that the detailed electronic components andfunctions of the circuit which are not important within the context ofthis invention, and which could easily be selected and determined by theexpert, are not all represented or described, so that the circuitsdescribed and represented certainly do not have to be considered ascompletely exhaustive with regard to the composition of the chipsobtained in practice.

What is claimed is:
 1. An electronic phase-shift keying modulatorcircuit comprising an input (1) intended to receive a sinusoidal inputsignal Se of angular frequency ωe and an output (2) delivering asinusoidal output signal Ss phase shifted with respect to the inputsignal by a value φj which can vary among m values, φ1, . . . , φj, . .. , φm, m being an integer greater than or equal to 2, in accordancewith a control signal SCj, the output signal Ss having an angularfrequency ωs that is independent of the control signal Scj, wherein saidcircuit comprises:a distribution line (6) extending from the input andincluding n cells Co, . . . , Ci, . . . , Cn-1, of similar phase shift,n being a whole number greater than or equal to 2, the n phase-shiftcells being mounted along the distribution line (6) with eachphase-shift cell Ci of rank i along the distribution line (6)comprising:an input, referred to as the series input ISi, receiving thesignal coming from the input of the circuit, either directly where i=0,or via (i-1) preceding phase-shift cells of rank less than i, interposedbetween the input (1) of the circuit and this phase-shift cell Ci, afirst output, referred to as the series output OSi, delivering thesignal on the distribution line to a subsequent phase-shift cell Ci+1 ofhigher rank i+1, or, where i=n-1, to a terminating device (7) of thedistribution line (6), a tapping point Ni of the distribution line (6),a second output, referred to as the branched output ODi, connected tothe tapping point Ni via a transistor Ti whose first terminal isconnected to the tapping point Ni, whose second terminal is connected toground, and whose third terminal supplies said branched output ODi ofthe phase-shift cell Ci, each phase-shift cell Ci being designed todeliver at its branched output ODi a signal SDi that is phase shiftedwith respect to the input signal Se, by the sum φ(Ci) of the phaseshifts successively applied to the input signal Se, from the input (1)of the circuit by the phase-shift cells interposed between the input (1)of the circuit and said branched output ODi, connected to said branchedoutput ODi of each phase-shift cell Ci, a switching/modulating circuitcontrolled by the control signal SCj, this switching/modulating circuitbeing:when n=m, a switching circuit (CO0, CO1) delivering either a zerosignal, or the signal SDi received from the cell Ci, in accordance withthe control signal SCj, when n≠m, a modulating circuit Mo, . . . , Mi, .. . , Mn-1 with p phase states, p being a whole number less than mchosen so that m≦p^(n), designed to phase-shift the signal SDi receivedfrom the phase-shift cell Ci by a value φk, k being a whole numbervarying between 1 and p, in accordance with the control signal SCj,means (5) for summing in phase the signals Ssi coming from nswitching/modulating circuits and to deliver at said output (2) of thecircuit the result of this sum which forms the output signal Ss.
 2. Thecircuit as claimed in claim 1, wherein each transistor Ti of thephase-shift cells is a field-effect transistor, and wherein said circuitcomprises means (10, 11) for biasing the field-effect transistors of thephase-shift cells.
 3. The circuit as claimed in claim 1, wherein eachtransistor Ti of the phase-shift cells is a field-effect transistorwhose:first terminal is the gate, second terminal is the source, thirdterminal is the drain,and wherein said circuit comprises means (12) forapplying a DC voltage whose value is adjustable at the tapping point Ni,so as to form an adjustable capacitance between the tapping point Ni andground.
 4. The circuit as claimed in claim 1, wherein all thephase-shift cells are functionally identical and generate the same phaseshift Δφ along the distribution line (6), the cell Ci delivering at itsbranched output a branched signal SDi that is phase-shifted with respectto the input signal Se by φ(Ci)=i×Δφ+ψ, where ψ is a constant.
 5. Thecircuit as claimed in claim 4, wherein Δφ=2π/m.
 6. The circuit asclaimed in claim 1, wherein said means (5) for summing in phase comprisestar-connection lines (33, 34), all of which have the same length, fromthe outputs of n switching/modulating circuits at a common output point.7. The circuit as claimed in claim 1, wherein said means (5) for summingin phase comprise a phase combiner circuit formed by a Wilkinson couplertree (25, 26, 27) the final apex of which forms said output (2) of thecircuit.
 8. The circuit as claimed in claim 1, wherein when m is amultiple of a power of 2, n is equal to a power of
 2. 9. The circuit asclaimed in claim 1, whereinm is greater than or equal to 4, p is equalto 1, 2 or
 4. 10. The circuit as claimed in claim 1, whereinm is greaterthan or equal to 8, n is greater than or equal to
 4. 11. The circuit asclaimed in claim 1, wherein the switching/modulating circuits aresimilar and consist exclusively of passive components.
 12. The circuitas claimed in claim 1, wherein p=2 and wherein the switching/modulationcircuits are binary phase-shift keying BPSK/modulator circuits withpassive components, each formed by a high-pass filter (18) and alow-pass filter (17) connected in parallel and whose outputs areswitched by a non-biased field-effect transistor array (21, 22) withtheir gate receiving a control signal having two complementary states.13. The circuit as claimed in claim 3, wherein each phase-shift cell Ciis of a series inductance and parallel capacitance type, wherein saidtransistor Ti of each phase-shift cell Ci is a biased field-effecttransistor whose gate is connected to the tapping point Ni on thedistribution line (6) in parallel with the inductance, whose source isconnected to ground, and whose drain supplies the branched signal SDi tosaid branched output ODi, and wherein said parallel capacitance is atleast partially made up of the capacitance formed between the gate andthe source of said biased field-effect transistor Ti.
 14. The circuit asclaimed in claim 13, wherein the means (12) for applying and adjusting aDC voltage of an adjustable value to each tapping point Ni include aterminal (12) of the distribution line (6) intended to receive a DCvoltage VA so that the phase shifts of the signal at each tapping pointNi of the phase-shift cells Ci can be adjusted simultaneously, inparticular in accordance with the angular frequency ωe, by setting thisone variable DC voltage VA.
 15. The circuit as claimed in claim 14,wherein it comprises means (13, 14, 15) forming a variable impedance atone end terminal of the distribution line (6) opposite to the input (4)of the circuit, to allow its impedance matching.
 16. The circuit asclaimed in claim 15, wherein the variable impedance comprises afield-effect transistor (15) configured as a variable resistance, andwhose gate receives a DC control voltage VR.
 17. The circuit as claimedin claim 1, wherein the frequency of the input signal is greater than 1Gigahertz and said circuit is formed from a monolithic integratedcircuit.